The invention relates to microcomputers.
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network, including for example connection to a host microcomputer for use in debugging routines. Such systems are also known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication on on-chips it is common for bit packets to be transmitted between modules on a chip in a bit parallel format. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Such microcomputers require access to instruction or code sequences and for efficient operation it is desirable for the instructions to be retrievable from locations within the address space of the CPU. One approach described in co-pending European patent application number 97308517.8 is to provide an on-chip external communication port forming part of the memory address space of the CPU from which instructions may be fetched and which translates between a parallel format on-chip and a less parallel format for off-chip communications.
This does not, however, address the issue of debugging the chip""s interfaces to external devices, such as displays or network connections, or the interfaces within the chip between the CPU(s) and other on-chip units. In a typical system the only convenient way to monitor the chip""s communications with these devices is to alter the software that the chip runs so as to copy those communications to a port from which an external computer can monitor them. However, since this involves changing the software it can be difficult to do, and bugs can be introduced when the alterations to the software are removed after debugging.
According to a first aspect of the present invention there is provided a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device; the integrated circuit chip having: an on-chip CPU with a plurality of registers; a communication bus for addressing a plurality of devices assigned to a single memory address space of the CPU and providing a parallel communication path between the CPU and a first memory local to the CPU; an address memory for storing the assignment of addresses to the plurality of devices; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby the port may be addressed by execution of an instruction by the CPU; the external computer device having a second memory local to the external computer device, which is accessible by the CPU through the port; and the computer system having address diversion means for reconfiguring the memory address space of the CPU so as to assign to the port memory addresses of another one of the devices.
According to a second aspect of the present invention there is provided a method of operating a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device; the integrated circuit chip having: an on-chip CPU with a plurality of registers; a communication bus for addressing a plurality of devices assigned to a single memory address space of the CPU and providing a parallel communication path between the CPU and a first memory local to the CPU; an address memory for storing the assignment of addresses to the plurality of devices; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby the port may be addressed by execution of an instruction by the CPU; the external computer device having a second memory local to the external computer device, which is accessible by the CPU through the port, the port; and the method comprising reconfiguring the memory address space of the CPU so as to assign to the port the memory addresses of another one of the devices.
Preferably the address memory is a programmable memory. The address diversion means may suitably reconfigure the memory address space of the CPU by reprogramming the address memory. The address diversion means may suitably reconfigure the memory address space of the CPU by redirecting to the port communications that specify memory addresses of the said other one of the devices. The address diversion means suitably comprises a program memory for storing a set of instructions for reconfiguring the memory address space of the CPU.
The external computer device suitably comprises the address diversion means. Alternatively, or in addition, the on-chip CPU may comprise the address diversion means.
The said other device may suitably be an input device and/or an output device. The said other device may comprise a memory which can be written to but not read by means of the communication bus. The communication bus preferably carries data in a packetised format.
Preferably the first memory has software for execution by said on-chip CPU and the second memory has software for execution by said on-chip CPU in a debugging routine for said on-chip CPU. Preferably the second memory has software for execution by said external computer device in a debugging routine for said on-chip CPU.
The said single integrated circuit chip may have a plurality of CPUs on the same chip each connected to the communication bus. By this means each CPU on the chip may suitably address the external port.
The first memory may be an external memory for the single integrated circuit chip. Preferably an on-chip cache is also provided on the integrated circuit chip.
The said step of reconfiguring the memory address space of the CPU suitably comprises reprogramming the address memory.
The external computer suitably performs the step of reconfiguring the memory address space of the CPU.
The step of reconfiguring the memory address space of the CPU suitably comprises redirecting to the memory addresses of the port communications that specify memory addresses of the said other one of the devices. The on-chip CPU suitably performs the step of reconfiguring the memory address space of the CPU.